A variable resistance material, such as a CMR (Colossal Magneto-Resistance) material, has such a property that a resistance value thereof largely changes depending on the magnitude and polarity of an applied voltage pulse, and this change is maintained even after the applied voltage is decreased. In recent years, a variable resistance element using the variable resistance material, and semiconductor devices, such as a nonvolatile memory using this variable resistance element, have been developed by utilizing the above property.
As one example, the variable resistance element is configured such that a thin film or a bulk material made of the variable resistance material is sandwiched between a pair of electrodes. In use, an electrical pulse is applied between the electrodes, and this changes the resistance value of the variable resistance material. For example, the application of a positive voltage pulse increases the resistance value (about 1 MΩ for example), and the application of a negative voltage pulse decreases the resistance value (about 1 kΩ for example). As above, the resistance value of the variable resistance material largely changes by the voltage pulse. Therefore, the variable resistance element can be utilized as, for example, a nonvolatile memory element by reading the resistance value using the electrodes.
One conventional variable resistance element and its manufacturing method are disclosed in Patent Document 1. FIG. 39 are cross-sectional views showing the schematic configuration of a variable resistance element array. FIG. 39(a) shows a cross section parallel to a bit line 28, and FIG. 39(b) shows a cross section parallel to a word line 23. As shown in FIG. 39, a plurality of variable resistance elements 50 are integrated to constitute a variable resistance element array 500. In the variable resistance element array 500, word lines that are N+ regions 23 are formed on a substrate 21 so as to be in parallel with each other at predetermined intervals. Elements each formed by stacking a P+ region 24, a barrier metal 25, a lower electrode 26, and a PCMO memory material (variable resistance material) 27 are formed on the respective N+ regions 23 at predetermined intervals, and spaces around the elements are filled with an interlayer insulating layer 22. The upper ends of the elements are connected to upper electrodes 28 (bit line) formed in parallel with each other at predetermined intervals. Since the word lines and the bit lines are orthogonal to each other, the elements are arranged in a matrix, and thereby this can be utilized as a memory array.
In a method for manufacturing the variable resistance element array 500, the PCMO memory materials 27 are deposited on the lower electrodes 26, the barrier metals 25, the P+ regions 24, and the N+ regions 23 formed on the substrate 21. The deposited PCMO memory materials 27 are smoothed by CMP (Chemical Mechanical Process), and the upper electrodes 28 are formed on the PCMO memory materials 27.
Patent Document 1: Japanese Laid-Open Patent Application Publication 2004-128486